设计自动化标准委员会

设计自动化标准委员会（英语：Design Automation Standards Committee, DASC）是由IEEE中对设计自动化感兴趣的人结成的子学会、IEEE计算机社团（Computer Society）和IEEE标准协会（IEEE Standards Association）共同组成。该组织负责监管有关计算机辅助设计（即设计自动化）的IEEE标准。它也是IEEE计算机社团的一部分

设计自动化委员会赞助的标准包括：

• IEEE 1076 Standard VHDL Language Reference Manual (VASG)[1]（页面存档备份，存于互联网档案馆）
  • VHDL-200x [2]（页面存档备份，存于互联网档案馆）: the next revision
  • Issues Screening and Analysis Committee (ISAC) [3]（页面存档备份，存于互联网档案馆）
  • VHDL Programming Language Interface Task Force (VHPI) [4]（页面存档备份，存于互联网档案馆）
  • P1076.1 Standard VHDL Analog and Mixed-Signal Extensions (VHDL-AMS)
  • P1076.1.1 Standard VHDL Analog and Mixed-Signal Extensions - Packages for Multiple Energy Domain Support (StdPkgs)
  • P1076.4 Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification (VITAL)
  • P1076.6 Standard for VHDL Register Transfer Level (RTL) Synthesis (SIWG)
• P1364.1 Standard for Verilog Register Transfer Level Synthesis (VLOG-Synth)
• P1481 Standard for Integrated Circuit (IC) Open Library Architecture (OLA) (IEEE1481R)
• P1499 Standard Interface for Hardware Description Models of Electronic Components (OMF)
• P1603 Standard for an Advanced Library Format (ALF) Describing Integrated Circuit (IC) Technology, Cells, and Blocks (ALF)
• P1647 Standard for the Functional Verification Language 'e' (eWG)
• P1666 Standard SystemC Language Reference Manual [cosponsored with IEEE-SA CAG]
• P1685 SPIRIT XML Standard for IP Description (IEEE-1685)
• P1735 (Study Group)
• SystemVerilog Working Group
  • P1800 SystemVerilog: Unified Hardware Design, Specification and Verification Language (SV-IEEE1800) [cosponsored with IEEE-SA CAG]
  • P1364 Standard for Verilog Hardware Description Language (IEEEVerilog)
• IEEE 1801 Standard for the Design and Verification of Low Power Integrated Circuits, the Unified Power Format
• IEEE 1850 Standard for PSL: Property Specification Language (cosponsored with IEEE-SA CAG)