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Sanshui, Foshan, Guangdong Province, China

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Advantages and Disadvantages

Pipelining does not help in all cases. There are several possible disadvantages. An instruction pipeline is said to be fully pipelined if it can accept a new instruction every clock cycle. A pipeline that is not fully pipelined has wait cycles that delay the progress of the pipeline.

并非在所有情况下管线技术都起作用。可能有一些缺点。如果一条指令管线能够在每一个时脉周期(clock cycle)接纳一条新的指令，被称为完整管线化(fully pipelined)。因管线中的指令需要延迟处理而要等待数个时脉周期，被称为非完整管线化。

Advantages of Pipelining:

1. The cycle time of the processor is reduced, thus increasing instruction issue-rate in most cases.

1. 减少了处理器执行指令所需要的时钟周期，在通常情况下增加了指令的输入频率(issue-rate)。

2. Some combinational circuits such as adders or multipliers can be made faster by adding more circuitry. If pipelining is used instead, it can save circuitry vs. a more complex combinational circuit.

2. 一些集成电路(combinational circuits)，例如加法器(adders)或者乘法器(multipliers)，通过添加更多的环路(circuitry)使其工作得更快。如果以管线化替代，能相对地减少环路。

Disadvantages of Pipelining:

1. A non-pipelined processor executes only a single instruction at a time. This prevents branch delays (in effect, every branch is delayed) and problems with serial instructions being executed concurrently. Consequently the design is simpler and cheaper to manufacture.

1. 非管线化的处理器每次(at a time)只执行一个指令。防止分支延时（事实上，每个分支都会产生延时）和串行指令被并行执行产生的问题。同时，设计比较简单和较低生产成本。

2. The instruction latency in a non-pipelined processor is slightly lower than in a pipelined equivalent. This is because extra flip flops must be added to the data path of a pipelined processor.

2. 在执行相同的指令时，非管线化处理器的指令传输延迟时间(The instruction latency)比管线化处理器明显较短。这是因为管线化的处理器必须在数据路径(data path)中添加额外正反器(flip-flops)。

3. A non-pipelined processor will have a stable instruction bandwidth. The performance of a pipelined processor is much harder to predict and may vary more widely between different programs.

3. 非管线化处理器有固定指令位宽(a stable instruction bandwidth)。管线化处理器的性能更难以预测，并且不同的程序之间的变化(vary)可能更大。

Execution is as follows: 执行顺序如以下列表所示

Generic pipeline

To the right is a generic pipeline with four stages:

  1. 讀取指令(Fetch)
  2. 指令解碼（Decode）
  3. 執行指令(Execute)
  4. 寫回執行结果(Write-back)

(for lw and sw memory is accessed after execute stage)

The top gray box is the list of instructions waiting to be executed; the bottom gray box is the list of instructions that have been completed; and the middle white box is the pipeline.

上方的大灰色方格是一连串未被执行的指令；下方的大灰色格是已被执行完成的指令；中间的大白色方格是管线。

Time Execution 时序执行情况 0 Four instructions are awaiting to be executed 四条指令等待执行 1

   * the green instruction is fetched from memory

从主存储器(memory)中读取绿色指令

2

   * the green instruction is decoded

绿色指令被解码

   * the purple instruction is fetched from memory

从主存储器中读取紫色指令 3

   * the green instruction is executed (actual operation is performed)

绿色指令被执行（事实上运算已经开始(performed)）

   * the purple instruction is decoded

紫色指令被解码

   * the blue instruction is fetched

从主存储器中读取蓝色指令 4

   * the green instruction's results are written back to the register file or memory

绿色指令的运算结果被写回到寄存器(register)或者主存储器

   * the purple instruction is executed

紫色指令被执行

   * the blue instruction is decoded

蓝色指令被解码

   * the red instruction is fetched

从主存储器中读取红色指令

5

   * the green instruction is completed

绿色指令被执行完毕

   * the purple instruction is written back

紫色指令的运算结果被写回到寄存器或者主存储器

   * the blue instruction is executed

蓝色指令被执行

   * the red instruction is decoded

红色指令被解码 6

   * The purple instruction is completed

紫色指令被执行完毕

   * the blue instruction is written back

蓝色指令的运算结果被写回到寄存器或者主存储器

   * the red instruction is executed

红色指令被执行 7

   * the blue instruction is completed

蓝色指令被执行完毕

   * the red instruction is written back

红色指令的运算结果被写回到寄存器或者主存储器 8

   * the red instruction is completed

红色指令被执行完毕 9 All instructions are executed

Bubble 气泡 A bubble in cycle 3 delays execution 一个气泡在编号为3的时脉周期中，指令执行被延迟 Main article: Bubble (computing)

When a "hiccup" in execution occurs, a "bubble" is created in the pipeline in which nothing useful happens. In cycle 2, the fetching of the purple instruction is delayed and the decoding stage in cycle 3 now contains a bubble. Everything "behind" the purple instruction is delayed as well but everything "ahead" of the purple instruction continues with execution.

在指令执行中产生一个“打嗝”(hiccup),在管线中生成一个没有实效的气泡。在编号为2的时脉周期中，紫色指令的读取被延迟，并且在编号为3的时脉周期中解码层也产生了一个气泡。所有在紫色指令之后的指令都被延迟执行，而在其之前已经执行了的指令则不受影响。

Clearly, when compared to the execution above, the bubble yields a total execution time of 8 clock ticks instead of 7.

由于气泡使指令执行延迟了一个时脉周期，完成全部4指令执行共需要8个时脉周期。

Bubbles are like stalls, in which nothing useful will happen for the fetch, decode, execute and writeback. It can be completed with a nop code.

Napier008

自我介绍

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